Programmable and erasable digital switch device and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S401000, C257SE29304, C257SE27103, C257SE21681, C438S213000, C438S279000, C438S287000, C438S288000, C438S264000, C365S185070, C365S185280

Reexamination Certificate

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11162893

ABSTRACT:
A programmable and erasable digital switch device is provided. An N-type memory transistor and a P-type memory transistor are formed over a substrate. The N-type memory transistor includes a first N-type doped region, a second N-type doped region, a first charge storage layer and a first control gate. The P-type memory transistor includes a first P-type doped region, a second P-type doped region, a second charge storage layer and a second control gate. A common bit line doped region is formed between the N-type memory transistor and the P type memory transistor and electrically connects the first N-type region to the second P-type doped region. A word line electrically connects the first control gate to the second control gate.

REFERENCES:
patent: 5538908 (1996-07-01), Kim
patent: 6200862 (2001-03-01), Gardner et al.
patent: 6448596 (2002-09-01), Kawajiri et al.
patent: 6548355 (2003-04-01), Pio
patent: 6916711 (2005-07-01), Yoo
patent: 7166887 (2007-01-01), Park et al.
patent: 2001/0001294 (2001-05-01), Pio
patent: 2004/0033664 (2004-02-01), Park
patent: 2004/0188754 (2004-09-01), Yoo

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