Methods for evaluating quality of test sequences for delay...

Details Methods for evaluating quality of test sequences for delay... Methods for evaluating quality of test sequences for delay...

2007-11-27

2007-11-27

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

10765276

ABSTRACT:
In evaluating of the quality of test sequences for delay faults, when all the delay faults are equally regarded, the process of detecting the delay faults deserving to be detected and those not so deserving to be detected cannot be reflected on the quality evaluation for the test sequences. To solve the problem, a “design delay value” on a signal path, on which a corresponding delay fault is defined, is weighted. This invention thus provides “methods of evaluating the quality of test sequences for delay faults” capable of evaluating the quality of the “delay fault test sequences” with more accuracy.

REFERENCES:
patent: 5748646 (1998-05-01), Hosokawa
patent: 6453437 (2002-09-01), Kapur et al.
patent: 6708139 (2004-03-01), Rearick et al.
Iyengar et al., “Delay test Generation 1—Concepts and Coverage Metrics,” IEEE, 1988, pp. 857-866.
Heragu et al., “Segment Delay Faults: A New Fault Model,” IEEE, 1996, pp. 39.

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