High performance embedded DRAM technology with strained silicon

Details High performance embedded DRAM technology with strained silicon High performance embedded DRAM technology with strained silicon

2007-08-28

2007-08-28

Vu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S386000

Reexamination Certificate

active

10541660

ABSTRACT:
Semiconductor devices are fabricated in a strained layer region and strained layer-free region of the same substrate. A first semiconductor device, such as a memory cell, e.g. a deep trench storage cell, is formed in a strained layer-free region of the substrate. A strained layer region is selectively formed in the same substrate. A second semiconductor device (66, 68, 70), such as an FET, e.g. an MOSFET logic device, is formed in the strained layer region.

REFERENCES:
patent: 5250448 (1993-10-01), Hamasaki et al.
patent: 5323031 (1994-06-01), Shoji et al.
patent: 6509587 (2003-01-01), Sugiyama et al.
patent: 6891209 (2005-05-01), Bulsara et al.
patent: 2003/0017667 (2003-01-01), Park et al.
patent: 2003/0030091 (2003-02-01), Bulsara et al.

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