Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-10-16
2007-10-16
Lindsay, Jr., Walter (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21345, C257SE21336, C257SE21427, C257SE21193
Reexamination Certificate
active
11092291
ABSTRACT:
A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.
REFERENCES:
patent: 5650340 (1997-07-01), Burr et al.
patent: 5817560 (1998-10-01), Gardner et al.
patent: 5908313 (1999-06-01), Chau et al.
patent: 6071783 (2000-06-01), Liang et al.
patent: 6162691 (2000-12-01), Huang
patent: 6265292 (2001-07-01), Parat et al.
patent: 6331467 (2001-12-01), Brown et al.
patent: 6368926 (2002-04-01), Wu
patent: 6489206 (2002-12-01), Chen et al.
patent: 6503833 (2003-01-01), Ajmera et al.
patent: 6605498 (2003-08-01), Murthy et al.
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6703648 (2004-03-01), Xiang et al.
patent: 6800899 (2004-10-01), Gonzalez
patent: 6815310 (2004-11-01), Roberds et al.
patent: 6821856 (2004-11-01), Takagi
patent: 6881635 (2005-04-01), Chidambarrao et al.
patent: 6921913 (2005-07-01), Yeo et al.
patent: 6946371 (2005-09-01), Langdo et al.
patent: 6949420 (2005-09-01), Yamashita
patent: 6960781 (2005-11-01), Currie et al.
patent: 6989570 (2006-01-01), Skotnicki et al.
patent: 7009226 (2006-03-01), Sun
patent: 7060585 (2006-06-01), Cohen et al.
patent: 7067379 (2006-06-01), Wen et al.
patent: 7118952 (2006-10-01), Chen et al.
patent: 7122449 (2006-10-01), Langdo et al.
patent: 7125774 (2006-10-01), Kim et al.
patent: 7157779 (2007-01-01), Nishibe et al.
patent: 2004/0045499 (2004-03-01), Langdo et al.
patent: 2004/0188760 (2004-09-01), Sckotnicki et al.
patent: 2006/0030093 (2006-02-01), Zhang et al.
Gannavaram, Shyam et al.; “Low Temperature (≦800 ° C.) Recessed Junction Selective Silicon-Germanium Source/Drain Technology for sub-70nm CMOS”; IEDM; 2000, pp. 18.3.1-18.3.4; IEEE, USA.
Chidambaram, P.R.; “35% Drive Current Improvement from Recessed-SiGe Drain Extensions on 37nm Gate Length PMOS”; Digest of Technical Papers, Symposium on VLSI Technology; 2004; pp. 48-49; IEEE; USA.
Dhandapani Veer
Nguyen Bich-Yen
Shiho Yasuhito
Thean Voon-Yew
Zhang Da
Dinh Thu-Huong
Freescale Semiconductor Inc.
Hill Daniel D.
King Robert L.
Lindsay, Jr. Walter
LandOfFree
Method for making a semiconductor device with strain... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for making a semiconductor device with strain..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making a semiconductor device with strain... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3850145