ESD protection structure with SiGe BJT devices

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S173000, C257S174000, C257S356000, C257S357000, C257S358000, C257S359000, C257S360000, C361S310000, C361S310000

Reexamination Certificate

active

11116807

ABSTRACT:
The present invention provides an ESD protection device or structure that exploits the high conductivity of a heavily doped heterojunction base of a standard SiGe bipolar junction transistor (BJT) cell. This improved ESD protection scheme further uses the combination of trench isolation and buried subcollector layer of the SiGe BJT to confine ESD current, minimizing parasitic substrate leakage and achieving large forward voltages while imposing minimal parasitic capacitive loads on a protected active device. Since the ESD protection structure is formed from conventional SiGe BJT transistor cells through modification of the contact metallization, it can be fabricated in an available SiGe BiCMOS fabrication process without additional processing steps, and characterization data already available for the SiGe BJTs can be used to model the performance of the ESD protection devices.

REFERENCES:
patent: 6803259 (2004-10-01), Lee
patent: 6815800 (2004-11-01), Mallikarjunaswamy
patent: 6984870 (2006-01-01), Kinayman
patent: 2005/0085028 (2005-04-01), Chatty et al.
patent: 2005/0225910 (2005-10-01), Stricker et al.
Shiao-Shien Chen et al., “Investigation of ESD Devices in 0.18-μm SiGe BiCMOS Process”, IEEE 41stAnnual International Reliability Physics Symposium, Dallas Texas (2003) pp. 357-360.
J. Dunn et al., “Trends in Silicon Germanium BiCMOS Integration and Reliability”, IEEE,THAnnual International Reliability Physics Symposium, San Jose California, (20000) pp. 237-242.
Steven H. Voldman et al., “The Influence of Process and Design of Subcollectors on the ESD Robustness of ESD Structures and Silicon Germanium Heterojunction Bipolar Transistors in a BiCMOS SiGe Technology”, IEEE, 03CH37400, 41STAnnual International Reliability Physics Symposium, Dallas Texas, (2003) pp. 347-356.
Steven H. Voldman et al., “Silicon Germanium Heterojunction Bipolar Transistor Electrostatic Discharge Power Clamps and the Johnson Limit in RF BICMOS SiGe Technology”, Elsevier Science, Journal of Electrostatics, vol. 56, (2002), pp. 341-362.
Steven H. Voldman, “The State of the Art of Electrostatic Discharge Protection: Physics, Technology, Circuits, Design, Simulation, and Scaling”, IEEE Journal of Solid-State Circuits, vol. 34, No. 9, (1999) pp. 1272-1282.
Albert Wang, “Recent Developments in ESD Protection for RFIC's”, IEEE (2003) pp. 171-178.

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