Tap with separate scan cell in series with instruction register

Details Tap with separate scan cell in series with instruction register Tap with separate scan cell in series with instruction register

2007-02-27

2007-02-27

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10962950

ABSTRACT:
An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

REFERENCES:
patent: 5968192 (1999-10-01), Kornachuk et al.
patent: 6000051 (1999-12-01), Nadeau-Dostie et al.
patent: 04077836 (1992-03-01), None

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