Semiconductor memory device with trench-type stacked cell...

Details Semiconductor memory device with trench-type stacked cell... Semiconductor memory device with trench-type stacked cell...

2007-10-23

2007-10-23

Pham, Hoai (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S508000

Reexamination Certificate

active

11650126

ABSTRACT:
A DRAM is provided that can reduce the parasitic capacitance between trench-type stacked cell capacitors in a memory cell region and suppress malfunction caused by noise. The trench-type stacked cell includes a number of capacitors having the same shape. The capacitors are formed in such a manner that storage nodes, a capacitor insulating film, and a plate electrode are buried in each of a plurality of trenches of an interlayer insulating film. The cell layout can be as follows: the capacitors are arranged so that only a part of a side face of one trench is opposite to that of the other; the capacitors are arranged so that the side face of one trench is opposite completely to that of the other and the distance between the opposing side faces is larger at the central portions of the respective trenches; or the cell is arranged so that the plate electrode is buried in a concavity between the cell capacitors.

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