Nonvolatile memory with spacer trapping structure

Details Nonvolatile memory with spacer trapping structure Nonvolatile memory with spacer trapping structure

2007-06-26

2007-06-26

Lee, Eugene (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C324S311000, C324S317000, C324S076490

Reexamination Certificate

active

10731517

ABSTRACT:
The present invention discloses a nonvolatile memory with spacer trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide. An isolation layer is formed over the sidewall of the gate structure. First spacers are formed on the sidewall of the isolation layer and becoming the spacer trapping structure for storing carrier. And the p-n junctions of source and drain regions are formed adjacent to the gate structure. Silicide is formed on the gate structure and the source and drain regions.

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