Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2007-08-21
2007-08-21
Estrada, Michelle (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C257SE21415, C438S164000, C438S233000
Reexamination Certificate
active
11146624
ABSTRACT:
A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.
REFERENCES:
patent: 5140391 (1992-08-01), Hayashi et al.
patent: 5188973 (1993-02-01), Omura et al.
patent: 5349228 (1994-09-01), Neudeck et al.
patent: 5773331 (1998-06-01), Solomon et al.
patent: 6492212 (2002-12-01), Ieong et al.
patent: 6580132 (2003-06-01), Chan et al.
patent: 6919647 (2005-07-01), Hackler et al.
patent: 7022562 (2006-04-01), Deleonibus
patent: 7176481 (2007-02-01), Chen et al.
patent: 2006/0110884 (2006-05-01), Wang et al.
patent: 2006/0151837 (2006-07-01), Chen et al.
Chan Kevin K.
Cohen Guy M.
Ieong Meikei
Roy Ronnen A.
Solomon Paul M
Estrada Michelle
International Business Machines - Corporation
Scully , Scott, Murphy & Presser, P.C.
Stark Jarrett J.
Tuchman, Esq. Ido
LandOfFree
Self-aligned isolation double-gate FET does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self-aligned isolation double-gate FET, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned isolation double-gate FET will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3831475