Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-06-19
2007-06-19
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
11032008
ABSTRACT:
An apparatus and method for transferring hidden signals in a boundary scan test interface is disclosed, which defines an invalid state transition loop in a boundary scan test interface and initially monitors an input of state transition diagram of the boundary scan test interface so that an output of a first data is generated when a first predetermined input stream conforming to the invalid state transition loop is detected, and then an output of a second data is generated when a second predetermined input stream is detected, wherein the second predetermined input stream is different from the first one and also conforms to the invalid state transition loop.
REFERENCES:
patent: 5768196 (1998-06-01), Bloker et al.
patent: 5898704 (1999-04-01), Kawano
patent: 6073254 (2000-06-01), Whetsel
patent: 6378090 (2002-04-01), Bhattacharya
patent: 7047467 (2006-05-01), Khu et al.
patent: 1089083 (2001-04-01), None
Bacon & Thomas PLLC
Sunplus Technology Co. Ltd.
Tu Christine T.
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