Scan test circuit including a control test mode

Details Scan test circuit including a control test mode Scan test circuit including a control test mode

2007-05-22

2007-05-22

Kerveros, James C (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

10127959

ABSTRACT:
A scan test circuit (100) including a path for capturing a control signal during a test mode is disclosed. Scan test circuit (100) may include a control supply circuit (20), a clock control circuit (30), a control signal test circuit (40), and a scan flip-flop (1). Control supply circuit (20) may receive a control signal (Enable signal), which may be used for enabling a clock signal (CLK) in a gated clock system. A control supply test circuit (40) may provide a signal path that can apply control signal (Enable signal) to scan flip-flop (1) for capturing. In this way, functionality of a combination circuit used for generating a control signal (Enable signal) may be verified.

REFERENCES:
patent: 6092226 (2000-07-01), Kramer et al.

Affiliated with

Also associated with

Rating

Scan test circuit including a control test mode does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Scan test circuit including a control test mode, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scan test circuit including a control test mode will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3824712