Address generator for block interleaving

Details Address generator for block interleaving Address generator for block interleaving

2007-11-20

2007-11-20

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Data formatting to improve error detection correction...

C714S701000

Reexamination Certificate

active

10971619

ABSTRACT:
A block interleaving/de-interleaving method and address generator thereof. The block interleaver segments the coded symbols into blocks according to a predetermined column value (C). The interleaver reads the coded symbols of each block by jumping according to the corresponding values (T0:TC-1) of a sequence matching table and the column value, and writes the values in sequence. The block de-interleaver reads the coded symbols sequentially, and re-assembles the coded symbols in the original order according to the same column value (C) and sequence matching table as the interleaver.

REFERENCES:
patent: 6691261 (2004-02-01), Ovalekar
patent: 6748561 (2004-06-01), Prasad
patent: 6986081 (2006-01-01), Furutani
patent: 01293074 (1989-11-01), None
Mathew et al., Algorithmic Foundations for a Parallel Vector Access Memory System, Jul. 2000, Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures SPAA'00, ACM Press, pp. 156-165.

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