Strained transistor with hybrid-strain inducing layer

Details Strained transistor with hybrid-strain inducing layer Strained transistor with hybrid-strain inducing layer

2007-01-16

2007-01-16

Dang, Trung (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE21409

Reexamination Certificate

active

11062723

ABSTRACT:
A semiconductor device having a hybrid-strained layer and a method of forming the same are discussed. The semiconductor device comprises: a gate dielectric over a substrate; a gate electrode over the gate dielectric; an optional pair of spacers along the sidewalls of the gate dielectric and the gate electrode; a source/drain region substantially aligned with an edge of the gate electrode; and a strained layer over the source/drain region, gate electrode, and spacers wherein the strained layer has a first portion and a second portion. The first portion of the strained layer is substantially over the source/drain region and has a first inherent strain. The second portion of the strained layer has at least a portion substantially over the gate electrode and the spacers and has a second inherent strain of the opposite type of the first strain.

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