Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-05-29
2007-05-29
Menz, Doug (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S302000, C257S315000, C257S329000, C257S314000
Reexamination Certificate
active
10231397
ABSTRACT:
A high density vertical single transistor gain cell is realized for DRAM operation. The gain cell includes a vertical transistor having a source region, a drain region, and a floating body region therebetween. A gate opposes the floating body region and is separated therefrom by a gate oxide on a first side of the vertical transistor. A floating body back gate opposes the floating body region on a second side of the vertical transistor and is separated therefrom by a dielectric to form a body capacitor.
REFERENCES:
patent: 4130892 (1978-12-01), Gunckel et al.
patent: 4826780 (1989-05-01), Takemoto et al.
patent: 4970689 (1990-11-01), Kenney
patent: 4999811 (1991-03-01), Banerjee
patent: 5006909 (1991-04-01), Kosa
patent: 5017504 (1991-05-01), Nishimura et al.
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5042011 (1991-08-01), Casper et al.
patent: 5066607 (1991-11-01), Banerjee
patent: 5122986 (1992-06-01), Lim et al.
patent: 5220530 (1993-06-01), Itoh
patent: 5280205 (1994-01-01), Green et al.
patent: 5291438 (1994-03-01), Witek et al.
patent: 5308783 (1994-05-01), Krautschneider et al.
patent: 5329481 (1994-07-01), Seevinck et al.
patent: 5378914 (1995-01-01), Ohzu et al.
patent: 5385853 (1995-01-01), Mohammad
patent: 5414288 (1995-05-01), Fitch et al.
patent: 5448513 (1995-09-01), Hu et al.
patent: 5519236 (1996-05-01), Ozaki
patent: 5574299 (1996-11-01), Kim
patent: 5627785 (1997-05-01), Gilliam et al.
patent: 5707885 (1998-01-01), Lim
patent: 5719409 (1998-02-01), Singh et al.
patent: 5732014 (1998-03-01), Forbes
patent: 5793686 (1998-08-01), Furutani et al.
patent: 5815432 (1998-09-01), Naffziger et al.
patent: 5854500 (1998-12-01), Krautschneider
patent: 5897351 (1999-04-01), Forbes
patent: 5909618 (1999-06-01), Forbes et al.
patent: 5936274 (1999-08-01), Forbes et al.
patent: 5937296 (1999-08-01), Arnold
patent: 5966319 (1999-10-01), Sato
patent: 5973356 (1999-10-01), Noble et al.
patent: 5991225 (1999-11-01), Forbes et al.
patent: 5995419 (1999-11-01), Trimberger
patent: 5998820 (1999-12-01), Chi
patent: 5999442 (1999-12-01), Van Der Sanden et al.
patent: 6031263 (2000-02-01), Forbes et al.
patent: 6072209 (2000-06-01), Noble et al.
patent: 6077745 (2000-06-01), Burns, Jr. et al.
patent: 6097065 (2000-08-01), Forbes et al.
patent: 6104061 (2000-08-01), Forbes et al.
patent: 6111286 (2000-08-01), Chi et al.
patent: 6118152 (2000-09-01), Yamaguchi et al.
patent: 6124729 (2000-09-01), Noble et al.
patent: 6143636 (2000-11-01), Forbes et al.
patent: 6150687 (2000-11-01), Noble et al.
patent: 6153468 (2000-11-01), Forbes et al.
patent: 6172390 (2001-01-01), Rupp et al.
patent: 6172901 (2001-01-01), Portacci
patent: 6191448 (2001-02-01), Forbes et al.
patent: 6204115 (2001-03-01), Cho
patent: 6238976 (2001-05-01), Noble et al.
patent: 6246083 (2001-06-01), Noble
patent: 6249020 (2001-06-01), Forbes et al.
patent: 6249460 (2001-06-01), Forbes et al.
patent: 6282115 (2001-08-01), Furukawa et al.
patent: 6307775 (2001-10-01), Forbes et al.
patent: 6316309 (2001-11-01), Holmes et al.
patent: 6350635 (2002-02-01), Noble et al.
patent: 6384448 (2002-05-01), Forbes
patent: 6399979 (2002-06-01), Noble et al.
patent: 6440801 (2002-08-01), Furukawa et al.
patent: 6456535 (2002-09-01), Forbes et al.
patent: 6492233 (2002-12-01), Forbes et al.
patent: 6501116 (2002-12-01), Kisu et al.
patent: 6504201 (2003-01-01), Noble et al.
patent: 6538916 (2003-03-01), Ohsawa
patent: 6549453 (2003-04-01), Wong
patent: 6556471 (2003-04-01), Chappell et al.
patent: 6560139 (2003-05-01), Ma et al.
patent: 6566682 (2003-05-01), Forbes
patent: 6611451 (2003-08-01), Houston
patent: 6624033 (2003-09-01), Noble
patent: 6661042 (2003-12-01), Hsu
patent: 6680864 (2004-01-01), Noble
patent: 6686624 (2004-02-01), Hsu
patent: 6710465 (2004-03-01), Song et al.
patent: 6727141 (2004-04-01), Bronner et al.
patent: 6750095 (2004-06-01), Bertagnoll et al.
patent: 6838723 (2005-01-01), Forbes
patent: 6940761 (2005-09-01), Forbes
patent: 6943083 (2005-09-01), Forbes
patent: 6956256 (2005-10-01), Forbes
patent: 6975531 (2005-12-01), Forbes
patent: 7030436 (2006-04-01), Forbes
patent: 2001/0028078 (2001-10-01), Noble
patent: 2001/0030338 (2001-10-01), Noble
patent: 2001/0032997 (2001-10-01), Forbes et al.
patent: 2001/0053096 (2001-12-01), Forbes et al.
patent: 2002/0098639 (2002-07-01), Kisu et al.
patent: 2002/0126536 (2002-09-01), Forbes et al.
patent: 2003/0001191 (2003-01-01), Forbes et al.
patent: 2003/0129001 (2003-07-01), Kisu et al.
patent: 2003/0205754 (2003-11-01), Forbes et al.
patent: 2004/0026728 (2004-02-01), Yoshida et al.
patent: 2004/0041236 (2004-03-01), Forbes
patent: 2005/0012130 (2005-01-01), Forbes
patent: 2005/0024936 (2005-02-01), Forbes
patent: 2005/0032313 (2005-02-01), Forbes
patent: 2005/0041457 (2005-02-01), Forbes
patent: 2005/0068828 (2005-03-01), Forbes
patent: 2005/0094453 (2005-05-01), Forbes
patent: 2005/0263763 (2005-12-01), Bhattacharyya
patent: 2005/0265069 (2005-12-01), Forbes
patent: 2006/0028859 (2006-02-01), Forbes
patent: 2006/0043411 (2006-03-01), Bhattacharayya
Mukai, M., et al., “A novel merged gain cell for logic compatible high density DRAMs”,1997 Symposium on VLSI Technology, Digest of Technical Papers,(Jun. 10-12, 1997), 155-156.
Adler, E. , et al., “The Evolution of IBM CMOS DRAM Technology”,IBM Journal of Research&Development, vol. 39, (1995), pp. 167-188.
Blalock, T. N., et al., “An Experimental 2T Cell RAM with 7 NS Access Time at Low Temperature”,IEEE, 1990 Symposium on VLSi Circuits, Alabama Microelectronics Science and Technology Center, Electrical Engineering Department, (1990),pp. 13-14.
Kim, Wonchan , et al., “A low-voltage multi-bit DRAM cell with a built-in gain stage”,Esscirc 93, Nineteenth European Solid-State Circuits Conference,(1995), 1 page.
Kim, W. , “An Experimental High-Density DRAM Cell with a Built-in Gain Stage”,IEEE Journal of Solid-State Circuits, vol. 29, No. 8, (1994), pp. 978-981.
Krautschneider, W.H. , et al., “Fully scalable gain memory cell for future DRAMs”,Microelectron Eng.(Netherlands), Microlelctronic Engineering, vol. 15, No. 1-4,(1991), 1 page.
Krautschneider, F., “Planar Gain Cell for Low Voltage Operation and Gigabit Memories”,Symposium on VLSI Technology Digest of Technical Papers,(1995), pp. 139-140.
Mukai, M , et al., “Proposal of a Logic Compatible Merged-Type Gain Cell for High Density Embedded . . . ”,IEEE Trans. on Electron Devices,(1999), 2 pages.
Ohsawa, T , “Memory design using one-transistor gain cell on SOI”,IEEE International Solid-State Circuits Conference. Digest of Technical Papers, vol. 1,(2002), pp. 152-455.
Okhonin, S , “A SOI capacitor-less 1T-DRAM concept”,2001 IEEE International SOI Conference. Proceedings, IEEE. 2001, (2000), pp. 153-154.
Rabaey, Jan M., “Digital integrated circuits : a design perspective”, Book, Published Upper Saddle River, N.J.: Prentrice Hall c1996,(1996), pp. 585-590.
Shukuri, S , “A complementary gain cell technology for sub-1 V supply DRAMs”,Electron Devices Meeting 1992, Technical Digest, (1992), pp. 1006-1009.
Shukuri, S. , “A Semi-Static Complementary Gain Cell Technology for Sub-1 V Supply DRAMs”,IEEE Transactions on Electron Devices, vol. 41, No. 6,(Jun. 1994), pp. 926-931.
Shukuri, S. , “Super-Low Voltage Operation of a Semi-Static Complementary Gain DRAM Memory Cell”,Symposium on VLSI Technology, Digest of Technical Papers,(1993), pp. 23-24.
Sunouchi, K , et al., “A self-amplifying (SEA) cell for future high density DRAMs”,International Electron Devices Meeting 1991. Technical Digest, (1991), pp. 465-468.
Takato, H. , et al., “Process Integration Trends for Embedded DRAM”,Proceedings of UISI Process Integration, Electrochemical Society Proceedings,99-18, (1999), 2 pages.
Terauchi, M. , “A Surrounding Gate Transistor (SGT) Gain Cell for Ultra High Density DRAMs”,1993 Symposium on VLSI Technology, Digest of Technical Papers,Kyoto, Jap
Menz Doug
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
LandOfFree
Single transistor vertical memory gain cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Single transistor vertical memory gain cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single transistor vertical memory gain cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3817622