Method of forming an integrated circuit incorporating higher...

Details Method of forming an integrated circuit incorporating higher... Method of forming an integrated circuit incorporating higher...

2007-06-12

2007-06-12

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S301000, C438S299000, C257SE21137

Reexamination Certificate

active

10924461

ABSTRACT:
A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a switch on a semiconductor substrate, and forming a driver switch of a driver embodied in a transistor. The method of forming the transistor includes forming a gate over the semiconductor substrate. The method of forming the transistor also includes forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate, and forming a heavily doped region adjacent the lightly doped region. The method of forming the transistor further includes forming an oppositely doped well under and within the channel region. The method of forming the transistor still further includes forming a doped region with a doping concentration profile less than the heavily doped region between the heavily doped region and the oppositely doped well.

REFERENCES:
patent: 4918026 (1990-04-01), Kosiak et al.
patent: 4947192 (1990-08-01), Hawkins et al.
patent: 5014098 (1991-05-01), Schlais et al.
patent: 5029283 (1991-07-01), Ellsworth et al.
patent: 5047358 (1991-09-01), Kosiak et al.
patent: 5156989 (1992-10-01), Williams et al.
patent: 5169794 (1992-12-01), Iranmanesh
patent: 5264782 (1993-11-01), Newton
patent: 5285369 (1994-02-01), Balakrishnan
patent: 5321319 (1994-06-01), Mahmood
patent: 5366916 (1994-11-01), Summe et al.
patent: 5469334 (1995-11-01), Balakrishnan
patent: 5485027 (1996-01-01), Williams et al.
patent: 5504450 (1996-04-01), McPartland
patent: 5610421 (1997-03-01), Contiero et al.
patent: 5644266 (1997-07-01), Chen et al.
patent: 5710054 (1998-01-01), Gardner et al.
patent: 5859606 (1999-01-01), Schrader et al.
patent: 5888861 (1999-03-01), Chien et al.
patent: 5889315 (1999-03-01), Farrenkopf et al.
patent: 5982645 (1999-11-01), Levran et al.
patent: 6005377 (1999-12-01), Chen et al.
patent: 6118351 (2000-09-01), Kossives et al.
patent: 6204542 (2001-03-01), Kinoshita et al.
patent: 6255714 (2001-07-01), Kossives et al.
patent: 6271063 (2001-08-01), Chan et al.
patent: 6288424 (2001-09-01), Ludikhuize
patent: 6297108 (2001-10-01), Chu
patent: 6380004 (2002-04-01), Boden et al.
patent: 6384447 (2002-05-01), Mihnea et al.
patent: 6384643 (2002-05-01), Grose et al.
patent: 6392275 (2002-05-01), Jang
patent: 6413806 (2002-07-01), Sicard et al.
patent: 6420771 (2002-07-01), Gregory
patent: 6495019 (2002-12-01), Filas et al.
patent: 6521960 (2003-02-01), Lee
patent: 6541819 (2003-04-01), Lotfi et al.
patent: 6545360 (2003-04-01), Ohkubo et al.
patent: 6551871 (2003-04-01), Takamura
patent: 6653174 (2003-11-01), Cho et al.
patent: 6744676 (2004-06-01), Leung et al.
patent: 6765272 (2004-07-01), Natsume
patent: 6833585 (2004-12-01), Kim et al.
patent: 6855985 (2005-02-01), Williams et al.
patent: 6900101 (2005-05-01), Lin
patent: 6911694 (2005-06-01), Negoro et al.
patent: 7012792 (2006-03-01), Yoshida
patent: 7015544 (2006-03-01), Lotfi et al.
patent: 2004/0094806 (2004-05-01), Schillaci et al.
patent: 2004/0227190 (2004-11-01), Cel et al.
patent: 2005/0167756 (2005-08-01), Lotfi et al.
patent: 2005/0168203 (2005-08-01), Dwarakanath et al.
patent: 2005/0168205 (2005-08-01), Dwarakanath et al.
patent: 2005/0169024 (2005-08-01), Dwarakanath et al.
patent: 2005/0179084 (2005-08-01), Robb et al.
patent: 2006/0027864 (2006-02-01), Negoro et al.
patent: 2006/0040441 (2006-02-01), Lotfi et al.
patent: 2006/0040449 (2006-02-01), Lotfi et al.
U.S. Appl. No. 10/766,983, filed Jan. 29, 2004, Dwarakanath et al.
U.S. Appl. No. 10/767,540, filed Jan. 29, 2004, Dwarakanath et al.
U.S. Appl. No. 10/767,684, filed Jan. 29, 2004, Lotfi et al.
U.S. Appl. No. 10/767,937, filed Jan. 29, 2004, Dwarakanath et al.
Betancourt-Zamora, R.J. et al., “A 1.5 mW, 200 MHz CMOS VCO for Wireless Biotelemetry,” First International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, Cancun, Mexico, pp. 72-74, Jul. 1997.
Goodman, J. et al., “An Energy/Security Scalable Encryption Processor Using an Embedded Variable Voltage DC/DC Converter,” IEEE Journal of Solid-State Circuits, vol. 33, No. 11 (Nov. 1998).
Horowitz, P., et al., “The Art of Electronics,” Second Edition, 1989, pp. 288-291, Cambridge University Press, Cambridge, MA.
Lotfi, A.W., et al., “Issues and Advances in High-Frequency Magnetics for Switching Power Supplies,” Proceedings of the IEEE, Jun. 2001, vol. 89, No. 6, pp. 833-845.

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