Semiconductor devices having a buried and enlarged contact...

Details Semiconductor devices having a buried and enlarged contact... Semiconductor devices having a buried and enlarged contact...

2007-11-20

2007-11-20

Pham, Thanhha S. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S774000, C257SE23145

Reexamination Certificate

active

11419719

ABSTRACT:
According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit line capping layer pattern stacked thereon. A buried contact interlayer insulating layer covers a surface of the semiconductor substrate having the two adjacent bit line patterns. A contact hole is placed in a portion between the bit line patterns to penetrate the buried contact interlayer insulating layer and the bit line interlayer insulating layer and to expose at least one side wall of the bit line patterns. A contact hole spacer covers side wall of the contact hole. A contact hole plug is placed on the contact hole spacer to fill the contact hole.

REFERENCES:
patent: 6020236 (2000-02-01), Lee et al.
patent: 6228762 (2001-05-01), Park
patent: 6383857 (2002-05-01), Terauchi et al.
patent: 6777305 (2004-08-01), Lee et al.
patent: 2002/0079536 (2002-06-01), Terauchi et al.
patent: 2002/0093042 (2002-07-01), Oh et al.
patent: 2004/0014278 (2004-01-01), Lee et al.
patent: 2004/0046251 (2004-03-01), Lee
patent: 2004/0188806 (2004-09-01), Chung et al.
patent: 2002-0002680 (2002-01-01), None
English language abstract of Korean Publication No. 2002-0002680.

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