Method of making dual damascene with via etch through

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S620000, C438S623000, C438S626000, C438S627000, C438S637000, C438S638000

Reexamination Certificate

active

10914394

ABSTRACT:
A method for fabricating dual damascene structures having improved IC performance and reduced RC delay characteristics is provided. In one embodiment, a substrate with an etch stop layer formed thereon is provided. A dielectric layer is formed on the etch stop layer and an anti-reflective coating layer is formed on the dielectric layer. A first patterned photoresist layer having a via hole pattern is formed on the anti-reflective coating layer. The via hole pattern is thereafter etched through the anti-reflective coating layer, the dielectric layer, and the etch stop layer to form a via hole. A sacrificial via fill layer is filled in the via hole. A second patterned photoresist layer having a trench pattern is formed above the sacrificial via fill layer. The trench pattern is etched into the sacrificial via fill layer, the anti-reflective coating layer, and the dielectric layer to form a trench. The sacrificial via fill layer is removed in the via hole. A conductive layer is thereafter formed in the via hole and trench.

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patent: 2005/0054194 (2005-03-01), Tsai et al.

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