Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-09-25
2007-09-25
Chen, Jack (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S266000
Reexamination Certificate
active
11162116
ABSTRACT:
A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.
REFERENCES:
patent: 2002/0185673 (2002-12-01), Hsu et al.
patent: 2003/0173646 (2003-09-01), Yang et al.
patent: 2006/0171206 (2006-08-01), Wong et al.
Article titled “Novel Bi-Directional Tunneling Program/Erase NOR (BiNOR)-Type Flash EEPROM” jointly authored by Yang et al., IEEE Transactions On Electron Devices vol. 46, No. 6, pp. 1294-1296, Jun. 1999.
Cho Chih-Chen
Wong Wei-Zhe
Yang Ching-Sung
Chen Jack
Jianq Chyun IP Office
Powerchip Semiconductor Corp.
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