Built-in self test circuitry for process monitor circuit for...

Details Built-in self test circuitry for process monitor circuit for... Built-in self test circuitry for process monitor circuit for...

2007-09-18

2007-09-18

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S745000

Reexamination Certificate

active

10954906

ABSTRACT:
A test circuitry approach which addresses the shortcoming associated with current process monitor circuitry. The approach provides a means of testing that can be employed in association with any and all tester platforms. On-chip built-in self test (BIST) circuitry is added to the design that analyzes the 10-bit value captured from the counter, and indicates to the ATE via a single pin at a single test vector location whether or not the device has passed its test limits. An alternative solution is to use the digital capture circuitry on a mixed-signal tester to capture the non-deterministic digital word generated by the process monitor circuitry, and then test that result against the desired test limits.

REFERENCES:
patent: 6751566 (2004-06-01), Sugai
patent: 6937051 (2005-08-01), Eichin et al.
patent: 7069488 (2006-06-01), Moll et al.
patent: 7084658 (2006-08-01), Saitou et al.
patent: 7085979 (2006-08-01), Kim et al.
patent: 7091728 (2006-08-01), Drouin et al.
patent: 2017333 (1994-07-01), None

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