Semiconductor storage device

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S104000

Reexamination Certificate

active

10747400

ABSTRACT:
A mask ROM small in circuit scale and low in consumption power has an n-type select transistor having a drain connected to a corresponding one of bit lines, a source connected to a data line, and a gate having a corresponding one of select signals input thereto. A p-type precharge transistor has a drain connected to a corresponding one of bit lines, a source connected to a power line, and a gate having a corresponding one of the select signals input thereto. Because the bit line is precharged by using a precharge transistor opposite in conductivity type to the select transistors, it is satisfactory to provide one precharge transistor for one bit line, greatly reducing the circuit scale.

REFERENCES:
patent: 4388702 (1983-06-01), Sheppard
patent: 4771284 (1988-09-01), Masleid et al.
patent: 5001668 (1991-03-01), Ito et al.
patent: 5018103 (1991-05-01), Pomper et al.
patent: 6404666 (2002-06-01), Uchida
patent: 6618282 (2003-09-01), Poplevine et al.
patent: 6738280 (2004-05-01), Satomi
patent: 04-209396 (1992-07-01), None
patent: 2002-323928 (2002-11-01), None

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