Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-09-18
2007-09-18
Smith, Matthew (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000, C257S357000, C257S390000, C257SE29129, C257SE27084
Reexamination Certificate
active
10934299
ABSTRACT:
A memory cell which is formed on a substrate of a first conductivity type. A pillar of the first conductivity type extends vertically upward from the substrate. A source region of a second conductivity type is formed in the substrate extending adjacent to and away from a base of the pillar. A drain region of the second conductivity type is formed in an upper region of the pillar. A gate dielectric and conductor are arranged along a first side of the pillar. A capacitor dielectric and body capacitor plate are arranged along an opposite, second side of the pillar. A depletion region around the source region defines a floating body region within the pillar which forms both a body of an access transistor structure and a plate of a capacitor structure. The cell also provides gain with respect to charge stored within the floating body.
REFERENCES:
patent: 5414287 (1995-05-01), Hong
patent: 5416350 (1995-05-01), Watanabe
patent: 5936274 (1999-08-01), Forbes et al.
patent: 5973356 (1999-10-01), Noble et al.
patent: 5991225 (1999-11-01), Forbes et al.
patent: 6072209 (2000-06-01), Noble et al.
patent: 6090661 (2000-07-01), Perng et al.
patent: 6097065 (2000-08-01), Forbes et al.
patent: 6124729 (2000-09-01), Noble et al.
patent: 6143636 (2000-11-01), Forbes et al.
patent: 6150687 (2000-11-01), Noble et al.
patent: 6153468 (2000-11-01), Forbes et al.
patent: 6174780 (2001-01-01), Robinson
patent: 6238976 (2001-05-01), Noble et al.
patent: 6246083 (2001-06-01), Noble
patent: 6352864 (2002-03-01), Lee
patent: 6538916 (2003-03-01), Ohsawa
patent: 6617651 (2003-09-01), Ohsawa
patent: 6661042 (2003-12-01), Hsu
patent: 6891225 (2005-05-01), Horiguchi et al.
patent: 2002/0024081 (2002-02-01), Gratz
patent: 2002/0028541 (2002-03-01), Lee et al.
patent: 2002/0038886 (2002-04-01), Mo
patent: 2004/0042256 (2004-03-01), Forbes
patent: 2004/0108532 (2004-06-01), Forbes
patent: 2004/0174734 (2004-09-01), Forbes
U.S. Appl. No. 10/739,253, filed Dec. 18, 2003, Leonard Forbes.
U.S. Appl. No. 10/808,058, filed Mar. 24, 2004, Leonard Forbes.
P. Fazan et al., “Capacitor-less 1-transistor DRAM”, IEEE International SOI Conference, 2002, pp. 10-13.
P.C. Fazan et al., “A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs”, Proceedings of the IEEE Custom integrated Circuits Conference 2002, pp. 99-102.
T. Ohsawa et al., “Memory Design Using a One-Transistor Gain Cell on SOI”, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, pp. 1510-1522, Nov. 2002.
Paul Kallender, “Swiss team develops single-transistor SOI DRAM cell”, http://www.eetimes.com/story/OEG20011016S0099, Oct. 16, 2001.
T. Ohsawa et al., “Memory Design Using One-Transistor Gain Cell on SOI”, IEEE Int. Solid State Circuits Conference, San Francisco, 2002, pp. 152-153.
T. Ohsawa et al., “A Memory Using One-Transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's” Symposium on VLSI Circuits, 2003, Jun. 12-14, pp. 93-96.
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
Pham Thanh V.
Smith Matthew
LandOfFree
High-density single transistor vertical memory gain cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with High-density single transistor vertical memory gain cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-density single transistor vertical memory gain cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3765432