Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2007-09-04
2007-09-04
Elms, Richard T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S239000, C365S230050
Reexamination Certificate
active
11357253
ABSTRACT:
Programmable logic devices may use shadow memory for gathering diagnostic information while testing memory blocks. Memory block testing may be performed at any clock speed allowed during normal operation in a system such as the highest allowed clock speed. Built in self test circuitry and address and data paths are formed by loading configuration data into a programmable logic device. During write operations on a memory block under test, test data words are written into the memory block. A comparator compares data words read from the memory block to expected data words received from the test pattern generator to produce corresponding comparison data words. The comparison data words are written into the shadow memory. The same addresses are applied to the memory block under test and the shadow memory, so the stored comparison data words form a test results bit map indicative of errors in the memory block.
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Altera Corporation
Elms Richard T.
Nguyen Hien
Treyz G. Victor
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