Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-05-01
2007-05-01
Knight, Anthony (Department: 2121)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S726000, C714S727000, C714S733000, C714S734000, C324S765010, C324S763010, C324S073100, C324S537000
Reexamination Certificate
active
11073964
ABSTRACT:
The invention is directed to an integrated circuit that includes a plurality of functional circuit blocks. Respective associated multiplexers are used to change over between a normal mode and a test mode. The input side of the multiplexers each have a test register connected thereto which is coupled to a serial bus. A control unit controls the transfer of test data to a selected function block on the basis of the state of a mode-of-operation memory cell in the respective test register. This means that there is little involvement required to put individual function blocks of a chip deliberately into a test mode and to program them as appropriate, while other function blocks are operating in normal mode. The principle described allows a high degree of flexibility with regard to the testing of integrated circuits with a multiplicity of functional assemblies.
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International Search Report, Int'l Application No. PCT/DE03/02772, Int'l Filing Date Aug. 20, 2003, 2 pgs.
Eschweiler & Associates LLC
Hartman, Jr. Ronald D.
Infineon - Technologies AG
Knight Anthony
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