Self aligned metal gates on high-k dielectrics

Details Self aligned metal gates on high-k dielectrics Self aligned metal gates on high-k dielectrics

2007-05-08

2007-05-08

Baumeister, B. William (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S387000, C257SE29266, C438S303000, C438S926000

Reexamination Certificate

active

11451703

ABSTRACT:
A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall spacers are formed adjacent to the sacrificial carbon gate, and source/drain regions for the transistor are formed using the sacrificial carbon sidewall spacers to define the source/drain regions. The sacrificial carbon sidewall spacers are replaced with non-carbon sidewall spacers, and the sacrificial carbon gate is replaced with a desired metal gate material to provide the desired metal gate material on the gate dielectric. Various embodiments form source/drain extensions after removing the carbon sidewall spacers and before replacing with non-carbon sidewall spacers. An etch barrier is used in various embodiments to separate the sacrificial carbon gate from the sacrificial carbon sidewall spacers. Other aspects and embodiments are provided herein.

REFERENCES:
patent: 4745082 (1988-05-01), Kwok
patent: 4994404 (1991-02-01), Sheng et al.
patent: 5391510 (1995-02-01), Hsu et al.
patent: 5920121 (1999-07-01), Forbes et al.
patent: 5960270 (1999-09-01), Misra et al.
patent: 6051486 (2000-04-01), Gardner
patent: 6080646 (2000-06-01), Wang
patent: 6083836 (2000-07-01), Rodder
patent: 6100176 (2000-08-01), Forbes et al.
patent: 6121126 (2000-09-01), Ahn et al.
patent: 6143655 (2000-11-01), Forbes et al.
patent: 6333255 (2001-12-01), Sekiguchi
patent: 6492694 (2002-12-01), Noble et al.
patent: 6495436 (2002-12-01), Ahn et al.
patent: 6500756 (2002-12-01), Bell et al.
patent: 6504224 (2003-01-01), Ahn et al.
patent: 6514828 (2003-02-01), Ahn et al.
patent: 6534420 (2003-03-01), Ahn et al.
patent: 6534868 (2003-03-01), Sekiguchi
patent: 6541859 (2003-04-01), Forbes et al.
patent: 6559017 (2003-05-01), Brown et al.
patent: 6573169 (2003-06-01), Noble et al.
patent: 6605514 (2003-08-01), Tabery et al.
patent: 6664154 (2003-12-01), Bell et al.
patent: 6727560 (2004-04-01), Pan et al.
patent: 6767795 (2004-07-01), Ahn et al.
patent: 6790791 (2004-09-01), Ahn et al.
patent: 6818519 (2004-11-01), Fang et al.
patent: 6844203 (2005-01-01), Ahn et al.
patent: 6849546 (2005-02-01), Tu et al.
patent: 6864164 (2005-03-01), Daksnina-Murthy et al.
patent: 6879017 (2005-04-01), Ahn et al.
patent: 6884739 (2005-04-01), Ahn et al.
patent: 6893984 (2005-05-01), Ahn et al.
patent: 6900122 (2005-05-01), Ahn et al.
patent: 7033869 (2006-04-01), Xiang et al.
patent: 2001/0003667 (2001-06-01), Ahn et al.
patent: 2002/0192974 (2002-12-01), Ahn et al.
patent: 2003/0043637 (2003-03-01), Forbes
patent: 2003/0045060 (2003-03-01), Ahn et al.
patent: 2003/0045078 (2003-03-01), Ahn et al.
patent: 2003/0119246 (2003-06-01), Ahn
patent: 2003/0119291 (2003-06-01), Ahn et al.
patent: 2003/0132491 (2003-07-01), Ahn
patent: 2003/0157764 (2003-08-01), Ahn et al.
patent: 2003/0207032 (2003-11-01), Ahn et al.
patent: 2003/0207540 (2003-11-01), Ahn et al.
patent: 2003/0227033 (2003-12-01), Ahn et al.
patent: 2003/0228747 (2003-12-01), Ahn et al.
patent: 2004/0023461 (2004-02-01), Ahn et al.
patent: 2004/0033704 (2004-02-01), Ahn et al.
patent: 2004/0038554 (2004-02-01), Ahn
patent: 2004/0043541 (2004-03-01), Ahn et al.
patent: 2004/0043569 (2004-03-01), Ahn et al.
patent: 2004/0110348 (2004-06-01), Ahn et al.
patent: 2004/0110391 (2004-06-01), Ahn et al.
patent: 2004/0142546 (2004-07-01), Kudo et al.
patent: 2004/0144980 (2004-07-01), Ahn et al.
patent: 2004/0175882 (2004-09-01), Ahn et al.
patent: 2004/0175910 (2004-09-01), Pan et al.
patent: 2004/0214399 (2004-10-01), Ahn et al.
patent: 2004/0262700 (2004-12-01), Ahn et al.
patent: 2005/0020017 (2005-01-01), Ahn et al.
patent: 2005/0051854 (2005-03-01), Cabral et al.
patent: 2005/0054165 (2005-03-01), Ahn et al.
patent: 2005/0077519 (2005-04-01), Ahn et al.
patent: 2005/0145894 (2005-07-01), Chau et al.
patent: 2005/0272191 (2005-12-01), Shah et al.
Huff et al., “High Dielectric Constant Materials,” Springer, 2005, pp. 261-266.
Ahn, Kie Y., “ALD of Amorphous Lanthanide Doped Tiox Films”, U.S. Appl. No. 11/092,072; filed Mar. 29, 2005 04-1321.
Ahn, Kie Y., “Atomic Layer Deposited Hafnium Tantalum Oxide Dielectrics”, U.S. Appl. No. 11/029,757; filed Jan. 5, 2005 04-0902.
Ahn, Kie Y., “Atomic Layer Deposited Lanthanum Aluminum Oxide Dielectric Layer”, U.S. Appl. No. 10/930,167; filed Aug. 31, 2004 04-0686.
Ahn, Kie Y., “Atomic Layer Deposited Lanthanum Hafnium Oxide Dielectrics”, U.S. Appl. No. 11/010,529; filed Dec. 13, 2004 04-0802.
Ahn, Kie Y., “Atomic Layer Deposited Titanium Aluminum Oxide Films”, U.S. Appl. No. 10/931,533; filed Aug. 31, 2004, client ref no 04-0579.
Ahn, Kie Y., “Atomic Layer Deposition of Hf3N4/HfO2 Films as Gate Dielectrics”, U.S. Appl. No. 11/063,717; filed Feb. 23, 2005, 04-1248.
Ahn, Kie Y., et al., “Atomic Layer Deposition of Zirconium-Doped Tantalum Oxide Films”, U.S. Appl. No. 10/909,959; filed Aug. 2, 2004.
Ahn, Kie Y., “Atomic Layer Deposition of Zr3N4/ZrO2 Films as Gate Dielectrics”, U.S. Appl. No. 11/058,563; filed Feb. 15, 2005.
Ahn, Kie Y., “Hybrid ALD-CVD of PrXOY/ZrO2 Films as Gate Dielectrics”, U.S. Appl. No. 11/010,766; filed Dec. 13, 2004, 04-0997.
Ahn, Kie Y., “Ruthenium Gate for a Lanthanide Oxide Dielectric Layer”, U.S. Appl. No. 10/926,812; filed Aug. 26, 2004, client ref no. 04-0538.
Anand, M., et al., “NURA: A Feasible, Gas-Dielectric Interconnect Process”,Symp. on VLSI Technology Digest of Technical Papers, (1996),82-83.
Harrison, S., et al., “Poly-gate REplacement Through Contact Hold (PRETCH); A new method for High-K/Metal gate and multi-oxide Implementation on chip”,IEEE Int. Electron Devices Meeting, Paper 12.2, San Francisco,(Dec. 2004), 4 pages.
Park, Chang S., et al., “MOS Characteristics of Substituted AI Gate on High-K Dielectric”,IEEE Electron Device Letters, vol. 25, No. 11, (Nov. 2004), 725-27.
Washburn, E.,International Critical Tables of Numerical Data Physics, Chemistry and Technology, 1, (2003), 103-105.

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