Controller for delay locked loop circuits

Details Controller for delay locked loop circuits Controller for delay locked loop circuits

2007-07-17

2007-07-17

Le, Thong Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100

Reexamination Certificate

active

09874898

ABSTRACT:
A method of controlling a delay locked loop (DLL) in a memory device is provided. The DLL generates an internal clock signal based on an external clock signal. The DLL constantly responds to variations in operating condition of the memory device to keep the external and internal clock synchronized. The method involves preventing the DLL from responding to a change in operating condition such as a change in the supply voltage of the memory device during an operational mode of the memory device such as an active mode, a read mode, or a refresh mode.

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