Power grid design for split-word line style memory cell

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S156000, C257S903000

Reexamination Certificate

active

11412752

ABSTRACT:
Disclosed is an improved power grid design for split-word line style memory cell. An array of memory cells comprises a first metal layer for local interconnections; a second metal layer for a bit line, a complementary bit line, and a first voltage line located between the bit line and the complementary bit line; a third metal layer for a first plurality of second voltage lines, and a word line located between the first plurality of second voltage lines, each running substantially in a first direction; and a fourth metal layer for a second plurality of second voltage lines, each running in a second direction orthogonal to the first direction.

REFERENCES:
patent: 6535453 (2003-03-01), Nii et al.
patent: 6590802 (2003-07-01), Nii

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