Memory interface control circuit

Details Memory interface control circuit Memory interface control circuit

2007-09-04

2007-09-04

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S193000, C365S194000, C365S233100

Reexamination Certificate

active

11384406

ABSTRACT:
The memory interface control circuit includes a mask-release-signal generation circuit which generates a basic mask-release signal from a data strobe signal input from a DRAM and a read timing signal indicative of a read start, a mask-release-signal generation circuit which generates a mask signal from a basic mask-release signal and a read mode signal indicative of a read mode of the DRAM, and a strobe signal generation circuit which generates an internal data strobe signal from a delayed data strobe signal and the mask signal. The mask of the data strobe signal alleviates gridge noise in the memory interface control circuit

REFERENCES:
patent: 6407963 (2002-06-01), Sonoda et al.
patent: 6621760 (2003-09-01), Ahmad et al.
patent: 7031205 (2006-04-01), Han et al.
patent: 7038953 (2006-05-01), Aoki
patent: 2001-189078 (2001-07-01), None
patent: 2004-092268 (2004-03-01), None

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