Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-03-06
2007-03-06
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C714S726000
Reexamination Certificate
active
10365999
ABSTRACT:
A method is provided for designing a semiconductor integrated circuit including a plurality of clock groups which are designed to be supplied with their respective clock signals. The method is improved by supplying plural kinds of clock signals for performing a scan testing respectively to the clock groups, the respective clock signals having different duty factors in at least a part of the clock groups. This prevents circuits on the plurality of scan lines from operating simultaneously, thus suppressing power consumption during a clock operation, allowing highly accurate testing.
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Garbowski Leigh M.
Hamre Schumann Mueller & Larson P.C.
Matsushita Electric - Industrial Co., Ltd.
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