Method of forming a memory cell array and a memory cell array

Details Method of forming a memory cell array and a memory cell array Method of forming a memory cell array and a memory cell array

2007-04-24

2007-04-24

Estrada, Michelle (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S211000, C438S294000, C438S296000, C438S201000, C438S222000, C257SE21646, C257SE21653

Reexamination Certificate

active

11140143

ABSTRACT:
A method of forming a memory cell array comprising a plurality of memory cells, each of the memory cells including a trench capacitor and a transistor is disclosed. In one embodiment, during the formation of the transistors, after the definition of isolation trenches and corresponding active areas, providing a gate electrode comprises etching the insulating material in the isolation trenches at a portion adjacent to the channel so that a portion of the channel is uncovered, the portion having the shape of ridge comprising a top side and two lateral sides, providing a gate insulating layer on the top side and the two lateral sides, providing a conducting material on the gate insulating layer so that as a result the gate electrode is disposed along the top side and the two lateral sides of the channel, wherein etching the insulating material in the isolation trenches is performed in which the insulating material is locally etched, wherein the insulating material in the upper portion of insulation grooves which separate active areas from each other is maintained.

REFERENCES:
patent: 2006/0056228 (2006-03-01), Schloesser et al.
C.H. Lee et al., “Novel Body Tied FinFET Cell Array Transistor DRAM with Negative Word Line Operation for sub 60nm Technology and beyond”, IEEE 2004, pp. 130-131.

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