Method and apparatus to store delay locked loop biasing...

Details Method and apparatus to store delay locked loop biasing... Method and apparatus to store delay locked loop biasing...

2007-07-31

2007-07-31

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S226000

Reexamination Certificate

active

10147838

ABSTRACT:
A calibration and adjustment system for post-fabrication control of a delay locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired delay locked loop performance characteristic after the delay locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the delay locked loop.

REFERENCES:
patent: 5727037 (1998-03-01), Maneatis
patent: 5757238 (1998-05-01), Ferraiolo et al.
patent: 6043717 (2000-03-01), Kurd
patent: 6166572 (2000-12-01), Yamaoka
patent: 6621315 (2003-09-01), Heo et al.
patent: 6928128 (2005-08-01), Sidiropoulos
“Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” by John G. Maneatis, IEEE Journal of Solid-State Circuits, vol. 31. No. 11, Nov. 1996 (10 pages).

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