Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2007-05-01
2007-05-01
Chung, Phung My (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S718000, C714S736000, C365S201000
Reexamination Certificate
active
10755503
ABSTRACT:
A new built-in self-test circuit device for testing an embedded memory array is achieved. The device comprises a pattern generator unit that executes a testing sequence to automatically write and read locations in an embedded memory. A comparison unit compares data read from the embedded memory and expected data provided by the pattern generator. An error signal is turned ON by the comparison unit when the data read does not match the data provided. An error release unit generates an error stop signal. The error stop signal is turned ON when the error signal is turned ON. The pattern generator unit testing sequence is stopped when the error stop signal is turned ON and is re-started when the error stop signal is turned OFF. The error stop signal is turned OFF when an external device asserts an error release signal.
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Chung Phung My
Taiwan Semiconductor Manufacturing Company
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