Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Multiplexing

Reexamination Certificate

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C365S230020

Reexamination Certificate

active

07151699

ABSTRACT:
Provided is a semiconductor memory device, which is capable of further simplifying the data multiplexing structure on a data write path, thereby preventing a timing mismatch in data input from being occurred. The semiconductor memory device, which comprises a data inputting block30for transferring data applied to a plurality of data input/output pins DQ0to DQ15to a plurality of global I/O buses gio<0:15>, a data multiplexing block32for multiplexing the data carried on the plurality of global I/O buses gio<0:15> according to a data width option, and a main write driver34, in response to a control signal, for driving the data outputted from the multiplexing means to a memory core region.

REFERENCES:
patent: 5504875 (1996-04-01), Mills et al.
patent: 6091667 (2000-07-01), Tanaka et al.
patent: 6687174 (2004-02-01), Maruyama et al.
patent: 6920068 (2005-07-01), Ku

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