Method of forming a MOS transistor with a layer of silicon...

Details Method of forming a MOS transistor with a layer of silicon... Method of forming a MOS transistor with a layer of silicon...

2006-08-29

2006-08-29

Brewster, William M. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S207000, C438S222000, C438S483000

Reexamination Certificate

active

07098095

ABSTRACT:
The vertical diffusion of dopants from the gate into the channel region, and the lateral diffusion of dopants from the source and drain regions into the channel region resulting from thermal cycling during the fabrication of a MOS transistor is minimized by forming the source and drain regions in a layer of silicon germanium carbon.

REFERENCES:
patent: 6103603 (2000-08-01), Han
patent: 6190975 (2001-02-01), Kubo et al.
patent: 6399970 (2002-06-01), Kubo et al.
patent: 6472685 (2002-10-01), Takagi
patent: 6492216 (2002-12-01), Yeo et al.
patent: 6512252 (2003-01-01), Takagi et al.
patent: 6597016 (2003-07-01), Yuki et al.
patent: 6707132 (2004-03-01), Banerjee et al.
patent: 2002/0163027 (2002-11-01), Skotnicki et al.
patent: 2002/0179946 (2002-12-01), Hara, et al.
patent: 2002/0182423 (2002-12-01), Chu et al.
Stanley Wolf, et al., “Silicon Processing For The VLSI Era”, vol. 1, Processing Technology, Lattice Press, 1986, pp. 155.

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