Method and apparatus for a register renaming structure

Details Method and apparatus for a register renaming structure Method and apparatus for a register renaming structure

2006-12-26

2006-12-26

Ellis, Richard L. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

Reexamination Certificate

active

07155599

ABSTRACT:
A processor having a register renaming structure and method is disclosed to recover a free list. The processor includes a physical register file including physical registers. The processor also includes a decoder to decode an instruction to indicate a destination logical register. The processor also includes a register allocation table to map the destination logical register to an allocated physical register. The processor also includes an active list that includes an old field and a new field. The old field includes at least one evicted physical register from the register alias table. The new field includes the allocated physical register. The processor also includes the free list of unallocated physical registers reclaimed from the active list.

REFERENCES:
patent: 5758112 (1998-05-01), Yeager et al.
Wallace, S et al., A scalable register file architecture for dynamically scheduled processors, Proceedings of the 1996 Conference on Parallel Architectures and Compilation Techniques, Oct. 1996, pp. 179-184.
Yeager, Kenneth C., The Mips R10000 superscalar microprocessor, IEEE Micro, Apr. 1996, v. 16, I. 2, pp. 28-41.
Moudgill, M. et al., Register renaming and dynamic speculation: an alternative approach, Proceedings of the 26th Annual International Symposium on Microarchitecture, Dec. 1-3, 1993, pp. 202-213.

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