Stacked die packaging and fabrication method

Details Stacked die packaging and fabrication method Stacked die packaging and fabrication method

2006-06-20

2006-06-20

Ho, Tu-Tu (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S686000, C257S777000

Reexamination Certificate

active

07064430

ABSTRACT:
A semiconductor package includes a substrate. A crenellated spacer is attached to the substrate. At least one top die is attached to the crenellated spacer. The at least one top die is wire bonded to the substrate, and an encapsulant is formed over the crenellated spacer and the at least one top die.

REFERENCES:
patent: 5963794 (1999-10-01), Fogal et al.
patent: 6215193 (2001-04-01), Tao et al.
patent: 6337226 (2002-01-01), Symons
patent: 6461897 (2002-10-01), Lin et al.
patent: 6633086 (2003-10-01), Peng et al.
patent: 2003/0038374 (2003-02-01), Shim et al.
patent: 2003/0047798 (2003-03-01), Halahan

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