Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-06-13
2006-06-13
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S057000
Reexamination Certificate
active
07062691
ABSTRACT:
There are provided a method and an apparatus for displaying test results and a recording medium, which allow easy detection of Devices for Testing in which probes are destroyed. The apparatus has two wafer probers, a work station, and a PC. On the basis of a display program and a display mode switching program stored in a ROM of the work station, respective test results of testing semiconductor chips by the two wafer probers are displayed on a CRT of the PC in correspondence to positions of the semiconductor chips on a wafer substrate, and, at the same time, a pass/fail ratio for each of the DFT's is displayed in parallel with the test results of the semiconductor chips.
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patent: 7-240445 (1995-09-01), None
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Chung Phung M.
Oki Electric Industry Co. Ltd.
Rabin & Berdo PC
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