Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-02-21
2006-02-21
Tran, Thien F. (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S203000, C438S204000, C438S205000, C438S309000, C438S313000, C438S322000, C438S323000, C438S340000
Reexamination Certificate
active
07001806
ABSTRACT:
A semiconductor structure comprises a buried first semiconductor layer of a first doping type, a second semiconductor layer of the first doping type on the buried semiconductor layer, which is less doped than the buried first semiconductor layer, a semiconductor area of a second doping type on the second semiconductor layer, so that a pn junction is formed between the semiconductor area and the second semiconductor layer, and a recess present below the semiconductor area in the buried first semiconductor layer, which comprises a semiconductor material of the first doping type, which can be less doped than the buried first semiconductor layer and has a larger distance to the semiconductor area of the second doping type on the second semiconductor layer, such that the breakdown voltage across the pn junction is higher than if the recess were not provided. Thereby, it is achieved that both a semiconductor structure with a desired breakdown voltage as well as a further semiconductor structure without this recess can be generated in the buried first semiconductor layer with optimized HF properties.
REFERENCES:
patent: 5121185 (1992-06-01), Tamba et al.
patent: 2002/0158308 (2002-10-01), Huber et al.
patent: 100 44 838 (2002-04-01), None
patent: 61-194845 (1986-08-01), None
O, Kenneth K., and Brad W. Scharf, “Effects of Buried Layer Geometry on Characteristics of Double Polysilicon Bipolar Transistors,” IEEE Electron Device Letters, vol., 19, No. 5, © May 1998, (3 pages).
Klein Wolfgang
Tilke Armin
Maginot Moore & Beck
Tran Thien F.
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