Memory units with normal and bit select write modes

Details Memory units with normal and bit select write modes Memory units with normal and bit select write modes

1988-03-09

1988-11-29

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, 365233, G11C 700, G11C 800, G11C 1134

Patent

active

047886668

ABSTRACT:
A memory unit includes a dual port memory provided with a RAS input terminal and a WB/WE input terminal adapted to receive a RAS clock signal and a bit select clock signal, respectively. A first signal generator generates the RAS clock signal and the bit select write signal of a timing, at which the dual port memory performs the normal write operation, whereas the bit select write operation is carried out in response to these clock signals supplied from a second signal generator at another timing. A selective one of the first and second signal generators is made operative in response to at least one bit mode-specifying data supplied from a CPU. Both of the first and second signal generators receive a continuous signal from CPU so that these signal generators are in a position to send the signals of different timings to the dual port memory responsive to the mode-specifying data.

REFERENCES:
patent: 4558433 (1985-12-01), Bernstein
patent: 4623990 (1986-11-01), Allen et al.

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