SOI device with different crystallographic orientations

Details SOI device with different crystallographic orientations SOI device with different crystallographic orientations

2006-11-07

2006-11-07

Lindsay, Jr., Walter L. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S244000, C438S386000, C438S387000

Reexamination Certificate

active

07132324

ABSTRACT:
A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.

REFERENCES:
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 5888864 (1999-03-01), Koh et al.
patent: 6426252 (2002-07-01), Radens et al.
patent: 6432774 (2002-08-01), Heo et al.
patent: 6566177 (2003-05-01), Radens et al.
patent: 6583462 (2003-06-01), Furukawa et al.
patent: 2005/0285175 (2005-12-01), Cheng et al.
U.S. Appl. No. 10/708,861 Entitled: Vertical Device with Optimal Trench Shape, filed Mar. 29, 2004.

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