Method and apparatus for saving current in a memory device

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S226000

Reexamination Certificate

active

07064992

ABSTRACT:
A memory device is configured to conserve electrical current by disabling the address lines provided to a memory bank when the address is not needed, such as during periods of automatic precharge. Because address data need not be provided while the memory bank is in an automatic precharge mode, the current used to keep the address lines active during this time may be conserved by suitably disabling the address lines for the duration of the automatic precharge. Disabling the various address lines may be accomplished by, for example, interposing an enabling element such as a field effect transistor within the address bus driver circuits leading to each memory bank, and by providing a suitable control signal to the enabling element to activate and deactivate the address line as needed.

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“Terms, Definitions, and Letter Symbols for Microcomputers, Microprocessors, and Memory Integrated Circuits”, JEDEC Standard; JESD 100-B, Dec. 1999, Electronic Industries Alliance.
“Double Data Rate (DDR) SRAM Specification”, JEDEC Standard; JESD 79; Jun. 2000; JEDEC Solid State Technology Association.

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