Method for the defect analysis of memory modules

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C714S718000

Reexamination Certificate

active

07124336

ABSTRACT:
A computer system has at least one data defect memory, at least one address defect memory and also a test program. The computer system is connected to a memory module that has a memory space with defect-free and defective memory cells, a plurality of data lines, and a plurality of address lines. The addresses of the defective memory cells in the memory space and the data lines that are connected to the defective memory cells are determined from the information items of the address defect memory and also from the information items of the data defect memory.

REFERENCES:
patent: 5062109 (1991-10-01), Ohshima et al.
patent: 5410687 (1995-04-01), Fujisaki et al.
patent: 5539699 (1996-07-01), Sato et al.
patent: 5909448 (1999-06-01), Takahashi
patent: 6449704 (2002-09-01), Takano
patent: 6477672 (2002-11-01), Satoh
patent: 196 80 964 (1997-03-01), None

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for the defect analysis of memory modules does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for the defect analysis of memory modules, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for the defect analysis of memory modules will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3669915

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.