Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-10-17
2006-10-17
Lamarre, Guy (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S718000
Reexamination Certificate
active
07124336
ABSTRACT:
A computer system has at least one data defect memory, at least one address defect memory and also a test program. The computer system is connected to a memory module that has a memory space with defect-free and defective memory cells, a plurality of data lines, and a plurality of address lines. The addresses of the defective memory cells in the memory space and the data lines that are connected to the defective memory cells are determined from the information items of the address defect memory and also from the information items of the data defect memory.
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Adler Frank
Versen Martin
Greenberg Laurence A.
Infineon - Technologies AG
Lamarre Guy
Locher Ralph E.
Stemer Werner H.
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