ROM error-correction control

Details ROM error-correction control ROM error-correction control

2006-06-27

2006-06-27

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Replacement of memory spare location, portion, or segment

C714S718000

Reexamination Certificate

active

07069482

ABSTRACT:
To determine the occurrence of an address for a defective memory, cell in a ROM, an error-correction control system includes a comparator that compares a set of incoming memory address signals with static signals provided by a laser-fuse array. The static signals represent addresses of defective memory cells in the ROM. An ADDHIT signal indicates that the ROM has received an address of a defective memory cell. The ADDHIT signal is then timed to provide a REV signal that changes the polarity of the memory bit signal out of a buffer circuit. This corrects an erroneous memory cell by reversing the sense of the memory bit received from a defective memory cell and delivered to an output terminal of the ROM. The REV signal is steered to an output buffer corresponding to the proper ROM chip output pad using a fuse-controlled selection circuit. A plurality of defective memory cells are corrected by using a number of comparators to compare input address signals to a number of fuse-controlled static addresses, each representing a defective memory cell.

REFERENCES:
patent: 4689792 (1987-08-01), Traynor
patent: 4984054 (1991-01-01), Yamada et al.
patent: 5920512 (1999-07-01), Larsen
patent: 5986952 (1999-11-01), McConnell et al.
patent: 6219286 (2001-04-01), Fuchigami et al.

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