Methods for forming semiconductor structures

Details Methods for forming semiconductor structures Methods for forming semiconductor structures

2006-08-29

2006-08-29

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S262000

Reexamination Certificate

active

07098105

ABSTRACT:
The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.

REFERENCES:
patent: 4234362 (1980-11-01), Riseman
patent: 4419809 (1983-12-01), Riseman et al.
patent: 4432132 (1984-02-01), Kinsbron et al.
patent: 4502914 (1985-03-01), Trumpp et al.
patent: 4648937 (1987-03-01), Ogura et al.
patent: 4776922 (1988-10-01), Bhattacharyya et al.
patent: 4838991 (1989-06-01), Cote et al.
patent: 5328810 (1994-07-01), Lowrey et al.
patent: 5502320 (1996-03-01), Yamada
patent: 5514885 (1996-05-01), Myrick
patent: 5905285 (1999-05-01), Gardner et al.
patent: 6004862 (1999-12-01), Kim et al.
patent: 6071789 (2000-06-01), Yang et al.
patent: 6291334 (2001-09-01), Somekh
patent: 6297554 (2001-10-01), Lin
patent: 6548396 (2003-04-01), Naik et al.
patent: 6573030 (2003-06-01), Fairbairn et al.
patent: 6627933 (2003-09-01), Juengling
patent: 6707092 (2004-03-01), Sasaki
patent: 6709807 (2004-03-01), Hallock et al.
patent: 6734063 (2004-05-01), Willer et al.
patent: 6734107 (2004-05-01), Lai et al.
patent: 6777725 (2004-08-01), Willer et al.
patent: 6936507 (2005-08-01), Tang et al.
patent: 2002/0004298 (2002-04-01), Bjamason et al.
patent: 2002/0125536 (2002-09-01), Iwasa et al.
patent: 2002/0130686 (2002-09-01), Forbes
patent: 2002/0135029 (2002-09-01), Ping et al.
patent: 2003/0008461 (2003-01-01), Forbes et al.
patent: 2003/0040186 (2003-02-01), Juengling et al.
patent: 2003/0042542 (2003-03-01), Maegawa et al.
patent: 2003/0044722 (2003-03-01), Hsu et al.
patent: 2003/0207207 (2003-11-01), Li
patent: 2003/0218199 (2003-11-01), Forbes et al.
patent: 2004/0000534 (2004-01-01), Lipinski
patent: 2004/0036095 (2004-02-01), Brown et al.
patent: 44 08 76 (1994-09-01), None
patent: 199 28 781 (2000-07-01), None
patent: WO 01/01489 (2001-01-01), None
patent: WO 02099864 (2002-12-01), None
patent: WO 2004/073044 (2004-08-01), None
U.S. Appl. No. 10/933,062, filed Sep. 1, 2004.
U.S. Appl. No. 10/934,778, filed Sep. 2, 2004.
Bergeron, et al., “Resolution Enhancement Techniques for the 90nm Technology Node and Beyond”, Future Fab International, Issue 15,4 pages.
Bhave et al., “Developer-soluble Gap fill materials for patterning metal trenches in Via-first Dual Damascene process”, preprint of Proceedings of SPIE: Advances in Resist Technology and Processing XXI, vol. 5376, John L. Sturtevant, editor, 2004, 8 pages.
Chung et al., “Pattern multiplication method and the uniformity of nanoscale multiple lines”, J. Vac.Sci. Technol. B21(4), Jul./Aug. 2003, pp. 1491-1495.
Chung et al., “Nanoscale Multi-Line Patterning Using Sidewall Structure”, Jpn., J.App.. Phys. vol. 41 (2002) Pt. 1, No. 6B, pp.4410-4414.
Joubert et al., “Nanometer scale linewidth control during etching of polysilicon gates in high-density plasmas”, Microelectronic Engineering 69 (2003), pp. 350-357.
Oehrlein et al., “Pattern transfer into low dielectic materials by high-density plasma etching”, Solid State Tech., May 2000, 8 pages.
Schloesser et al., “Highly Scalable Sub-50nm Vertical Double Gate Trench DRAM Cell”, Memory Development Center, Infineon Tech., 2004, 4 pages.
Copy of Written Opinion and International Search Report; PCT/US2005/017156.
International Search Report and Written Opinion in International Application PCT/US2005/030677.
Yan R-H et al., “Scaling the Si MOSFET: From Bulk to SOI to Bulk”, IEEE Transactions on Electron Devices USA; vol. 39, No. 7, Jul. 1992, pp. 1704-1710.
Sakao M. et al., “A Straight-Line-Trench Isolation and Trench-Gate Transistor (SLIT) Cell for Giga-bit DRAMs”, Proceedings of IEEE VLSI Technology Symposium May 17-19, 1993 Kyoto, Japan, May 17, 1993, pp. 19-20.

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