Reduction of lateral silicide growth in integrated circuit...

Details Reduction of lateral silicide growth in integrated circuit... Reduction of lateral silicide growth in integrated circuit...

2006-06-20

2006-06-20

Geyer, Scott (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S299000, C438S663000, C438S664000

Reexamination Certificate

active

07064067

ABSTRACT:
A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed around the gate. Source/drain junctions are formed in the semiconductor substrate. An intermediate phase silicide is formed on the source/drain regions and on the gate. The sidewall spacer is removed. A final phase silicide is formed from the intermediate phase silicide. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed in the interlayer dielectric to the final phase silicide.

REFERENCES:
patent: 6083847 (2000-07-01), Kuo
patent: 6603180 (2003-08-01), Gardner et al.
patent: 6797593 (2004-09-01), Chakravarthi et al.
patent: 6864143 (2005-03-01), Shue et al.

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