Semiconductor device and method for fabricating the same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S279000

Reexamination Certificate

active

07084026

ABSTRACT:
A region of an Si layer15located between source and drain regions19and20is an Si body region21which contains an n-type impurity of high concentration. An Si layer16and an SiGe layer17are, in an as grown state, undoped layers into which no n-type impurity is doped. Regions of the Si layer16and the SiGe layer17located between the source and drain regions19and20are an Si buffer region22and an SiGe channel region23, respectively, which contain the n-type impurity of low concentration. A region of an Si film18located directly under a gate insulating film12is an Si cap region24into which a p-type impurity (5×1017atoms·cm−3) is doped. Accordingly, a semiconductor device in which an increase in threshold voltage is suppressed can be achieved.

REFERENCES:
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patent: 6620665 (2003-09-01), Sugahara et al.
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patent: 9-97899 (1997-04-01), None
patent: 10-163342 (1998-06-01), None
“SiGe-Channel Heterojunction p-MOSFET's” , Sophie Verdonckt-Vanderbroek et al, IEEE Transactions on Electron Devices, vol. 41, No. 1, Jan. 1994, pp. 91-101.

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