Integrated circuit pattern designing method, exposure mask...

Details Integrated circuit pattern designing method, exposure mask... Integrated circuit pattern designing method, exposure mask...

2006-10-31

2006-10-31

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07131106

ABSTRACT:
There is disclosed a method of designing a pattern of an integrated circuit comprising calculating the window of lithography process on a substrate, the window being calculated at least in partial data of first design data for designing the circuit pattern of integrated circuit, and the window being also calculated in consideration of a specification value of an exposure mask for use in transfer of the circuit pattern, comparing the calculated window of lithography process and the window of lithography process actually required, revising the partial data when the calculated window is smaller than the actually required window, the partial data being revised such that the window of lithography process on the substrate is equal to or larger than the actually required window, and preparing second design data, the second design data being prepared by updating the first design data by using the revised partial data.

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Imai et al.,“A New Filtering Method to Extract Repeated Defects (FIMER)”, Jun. 1999, 4th International Work Statistical Metrology (IWSM), paper digest, pp. 22-25.
Kotani et al.; “Method of Setting Process Parameter and Method of Setting Process Parameter and/or Design Rule”; U.S. Appl. No. 10/385,628, filed Mar. 12, 2003.
Notification of Reasons for Rejection issued by the Japanese Patent Office for Japanese Patent Application Serial No. 2002-325478, and English translation thereof.

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