Memory device for compensating for a clock skew causing a...

Details Memory device for compensating for a clock skew causing a... Memory device for compensating for a clock skew causing a...

2006-11-28

2006-11-28

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S400000, C713S600000

Reexamination Certificate

active

07143303

ABSTRACT:
The present invention comprises a memory device for compensating for a clock skew that generates a centering error, and a method of compensating for the clock skew. To compensate for a clock skew that causes a centering error between an external clock signal and an output data signal, the memory device includes a phase detector (PD) and an up-down counter. The PD detects a phase difference between the output data signal and the external clock signal and generates an up signal or a down signal depending on the detected phase difference. The up-down counter is enabled by a calibration signal that directs a compensation of the skew and generates an offset code in response to the up signal or the down signal. The offset code is fed back to a delay locked loop (DLL) circuit and aligns the middle points of the output data signal with the edges of the external clock signal.

REFERENCES:
patent: 5935257 (1999-08-01), Nishimura
patent: 6121815 (2000-09-01), Terada et al.
patent: 6622255 (2003-09-01), Kurd et al.
patent: 6738922 (2004-05-01), Warwar et al.
patent: 7046060 (2006-05-01), Minzoni et al.
patent: 7076377 (2006-07-01), Kim et al.

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