Cell structure of EPROM device and method for fabricating...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S319000, C257S320000

Reexamination Certificate

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07053443

ABSTRACT:
Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack. Thus, ultraviolet rays can penetrate through the window and easily erase charges of the programmed cell.

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patent: 6327187 (2001-12-01), Bergemont et al.
patent: 6774431 (2004-08-01), Rudeck
patent: 6849506 (2005-02-01), Na et al.
patent: 11-111866 (1999-04-01), None

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