Apparatus having pattern scrambler for testing a...

Details Apparatus having pattern scrambler for testing a... Apparatus having pattern scrambler for testing a...

2006-02-21

2006-02-21

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S734000

Reexamination Certificate

active

07003697

ABSTRACT:
A system and method are provided for testing electronic devices. Generally, the system includes: (i) a pattern memory with outputs for storing and outputting bits to the device; and (ii) a pattern scrambler for coupling bits from the outputs to pins on the device to provide a test pattern to the device having a width of from 1 bit to a width equal to the number of outputs. Preferably, the system includes a clock with a clock cycle, and the scrambler can change the width and/or depth of the test pattern on a cycle-by-cycle basis More preferably, the scrambler can change the bits coupled to one or more of the pins on a cycle-by-cycle basis. In one embodiment, the memory simultaneously provides logic vector memory and scan memory for storing logic and scan vectors respectively, and the width/depth of the vectors can be changed on a cycle-by-cycle basis.

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Virgil P. Labuda et al. , “DFT Standards Allow Optimized Tester Configuration to Reduce Cost of Test”, The Second Annual IEEE ASIC Seminar and Exhibit. Sep. 25-28, 1989. Rochester Riverside Convention Center, Rochester, New York. IEEE Catalog # 89TH0280-8.

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