Memory system, module and register

Details Memory system, module and register Memory system, module and register

2006-05-23

2006-05-23

Butler, Dennis M. (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S503000, C713S600000

Reexamination Certificate

active

07051225

ABSTRACT:
Disclosed are a memory command address system and a memory module that can be operated not only for 266 MHzCLK but also for 200 MHzCLK, in which clock timings in the input sections of a PLL, a register, and a DRAM are matched to one another, a DLL (delay locked loop) is provided in the register, the output timing of CA signal from the register is controlled so that the setup time margin and the hold time margin of the CA signal with respect to the clock signal with the additional latency in the DRAM=1.5 or 2.0 are equated to each other, such that clock operation of 266 MHz, for example, is made possible. If both 266 MHz and 200 MHz are used, by taking account of the timing budget, control is made for retarding the timing of the CA signal input to the flip-flop which receives an internal clock signal (intCLK) supplied to the flip-flop for determining the CA signal output timing from the register. Alternatively, control is made for switching between the replica (replical) provided in the register and an output unit associated with the replica, depending on the frequency being used, so as to cope with both frequencies simply by providing one sort of the module and one sort of the register.

REFERENCES:
patent: 5883736 (1999-03-01), Oshima et al.
patent: 6397494 (2002-06-01), Slangen
patent: 6438066 (2002-08-01), Ooishi et al.
patent: 6549484 (2003-04-01), Morita et al.
patent: 6605969 (2003-08-01), Mikhalev et al.
patent: 6707726 (2004-03-01), Nishio et al.
patent: 6742098 (2004-05-01), Halbert et al.
patent: 0585005 (1994-03-01), None
patent: 1143645 (2001-10-01), None
patent: P2001-093300 (2001-04-01), None
patent: P2001-351380 (2001-12-01), None
patent: P2002-133867 (2002-05-01), None
patent: P2003-044349 (2003-02-01), None
patent: P2003-44350 (2003-02-01), None
patent: P2004-070800 (2004-03-01), None
European Search Report dated Jul. 6, 2005.
Untranslated Office Action issued by Japanese Patent Office on Jul. 26, 2005 in connection with corresponding Japanese application no. 2002-147486.
English translation of relevant portion of Examiner's comments in Japanese Office Action issued Jul. 26, 2005 submitted in lieu of statement of relevancy of prior art to present invention.

Affiliated with

Also associated with

Rating

Memory system, module and register does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory system, module and register, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory system, module and register will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3647027